1. Field of the Invention
The present invention relates generally to a shared memory subsystem for computer systems and, more particularly, to a shared memory subsystem that can be used for the main memory of the computer system for peripheral devices, such as, a display device.
2. Description of the Background Art
A typical personal computer system has a central processing unit (CPU) with a main memory and a graphics display subsystem with its own memory subsystem. Part of this memory subsystem is a frame buffer that provides the output to the display and part of this subsystem may be used for off-screen operations. However, even the off-screen memory is not part of the main system's pool of memory.
Another typical personal computer system has a single memory subsystem for both the CPU and the graphics subsystem. The performance of this type of computer system is lower than that of computer systems that have separate memory subsystems for the graphics display subsystem and for the CPU. Even though these single memory systems can support a cache memory for the CPU, the overall system performance is still lower because the memory bandwidth is shared between the graphics and CPU subsystems. These computer systems are very limited in their ability to allocate and share areas of memory between the two subsystems and typically require a "static" allocation of the memory areas to either the graphics display or CPU subsystem. The entire memory pool or portions of the memory pool cannot be dynamically switched between the CPU and the graphics display subsystems. These limitations are primarily because the display subsystem cannot address all of the memory space.
For systems that use a single memory subsystem to perform all of the display refresh and drawing operations, performance is compromised by the sharing of the memory bandwidth for these operations along with the CPU's need for memory bandwidth. "Refresh" is the general term for taking the information contained in a frame buffer memory and sequentially transferring rows of information to a palette digital-to-analog converter (DAC) to be displayed on an output device such as a monitor, TV or flat panel display. The entire contents of the frame buffer need to be transferred to the output device continuously for the display to be visible. In the case of a monitor, this is typically between 75 and 95 times per second. For high-resolution color systems, the refresh process may consume an appreciable portion of the total bandwidth available from the memory.
In addition to the refresh bandwidth, the graphics subsystem performs drawing operations that also consume an appreciable amount of bandwidth. In the case of 2D graphics acceleration the drawing operations include Bit-BLt (Bit Block Transfers), line drawing and other operations that use the same common pool of memory.
Intel, and other companies in the PC industry have designed an advanced peripheral port (AGP) bus and an associated system architecture for combining graphics and chipsets. AGP is a second private bus between the main memory controller chipset and the graphics display subsystems. While the CPU can access both the main memory system and the memory associated with the graphics subsystem, the memory associated with the graphics subsystem is not part of the CPU's executable pool of memory and the other peripherals are not able to access the graphics subsystem memory. AGP and the associated system architecture do allow for the storage of 3D texture memory in the main memory that can be accessed by the graphics subsystem. This is one limited use of shared main memory for a graphics function.
AGP is designed to overcome the above-described performance limitations that result when using the main memory subsystem for display refresh and drawing operations. AGP systems overcome this limitation by a brute force requirement that the graphics subsystem on the AGP bus have a separate frame buffer memory subsystem for screen refresh and drawing operations. While the CPU does have some limited read and write access to the frame buffer memory of the graphics subsystem, the CPU can never treat the graphics subsystem memory as a logical extension of the main system memory. The CPU can neither statically nor dynamically allocate the frame buffer subsystem memory as cacheable system memory.
Using frame buffer memory is a good solution for eliminating the performance penalties associated with drawing and refresh operations. However, the specialization of the frame buffer memory reduces its suitability to be fully utilized by the system and thus eliminates one of the primary benefits of the common memory subsystem. Meanwhile, as a frame buffer is always required, AGP systems do not allow for screen refresh to be performed from the main system memory. Additionally, the drawing operations must be performed in the graphics display memory and are therefore performed by the graphics subsystem controller.
Separating the frame buffer memory from the main system memory results in duplicating the input/output (I/O) system data. For example, this occurs in a system where either compressed or encoded video data enters the system over an I/O bus through a system controller and then is stored in the main system memory. If the data is displayed, it needs to be copied into the frame buffer. This results in a second copy of the data, transfer of which requires additional bandwidth.
Another alternative is to have a peripheral bus associated with the graphics controller where the I/O data is transferred to the frame buffer. While this allows display of the data without additional transfers over a system bus, the data remains local to the display subsystem. The CPU or main I/O systems do not have access to the data without using a system bus. For a shared memory subsystem, the I/O data enters the shared memory region. It is then available to either the display subsystem or the CPU.
FIG. 1 shows a diagram of a standard prior art memory architecture 100. A CPU subsystem 102 is connected to a subsystem 104 which is connected to a system Random Access Memory (RAM) 110 and to a peripheral component interface (PCI) bus 112. Subsystem 104 contains a system controller 106 and a graphics controller 108 that is connected to a display (not shown in FIG. 1). The system has a single memory subsystem for both the graphics display and CPU 102.
FIG. 2 is a diagram of the current state of art personal computer memory architecture 200 having separate memories for the CPU and for the graphics display. A CPU subsystem 204 is connected to a system controller 206 that is connected to a system RAM 210 and to a PCI bus 216. System controller 206 is also connected through a dedicated AGP bus 214 to a graphics controller 208 that is connected to a graphics RAM 212 and to a display 202. CPU subsystem 204 can not treat graphics RAM 212 as an extension of system RAM 210, and graphics subsystem 208 can not use system memory 210 for display refresh.
What is needed is a memory architecture in which common memory can be used for display memory and main memory, without having inadequate bandwidth access to the common memory impair performance.